Instruction Timing (was: Assembly or ....)

[Ron Widell]

In article <960 at vsi.COM> friedl at vsi.COM (Stephen J. Friedl) writes:
>In article <1988Nov29.181235.23628 at utzoo.uucp>, henry at utzoo.uucp
	(Henry Spencer) writes:
>> Alas, if you buy your newer faster CPUs from Motorola or Intel, they can't
>> tell you how many cycles each instruction takes!
>
>Why is this? [...] Is it laziness on the vendor's part or are there
>good reasons for this?

Some of the reasons are cache-hit-rate, alignment (of both instructions
and operands), instruction stream mix (and consequent overlap of the
execution unit with the bus controller) and operand dependencies (e.g.
multiply or divide).

While this is hardly an all-inclusive list, you probably get the idea:
too many variables.

>Stephen J. Friedl        3B2-kind-of-guy            friedl at vsi.com

-- 
Ron Widell, Field Applications Eng.	|UUCP: motmpl!ron
Motorola Semiconductor Products, Inc.,	|Voice:(612)941-6800
9600 W. 76th St., Suite G		| If they *knew* what I was saying,
Eden Prairie, Mn. 55344 -3718		| do you think they'd let me say it?