Languages vs. machines (was Re: The need for D-scussion)

[Eddie Wyatt]

 > I believe you folks are talking about the TF-1 processor.
 > The head architect of that recently gave a talk at CMU, and I think
 > I can remember some of the details:
 > 
 > About 32000 processors, total floating point computation speed 1 Tflops.
 > Every processor has 2 computation elements that are checked for
 > consistency to spot errors.  Any inconsistency takes the element off-line.
 > 
 > Total power about 3.5 MW.  Yes, powering the system up is interesting
 > (so is cooling).
 > Implementation is CMOS.  That means that if the system clock dies
 > at the full operating speed of something like 20 MHz or so, the
 > dI/dt current change melts the power lines and blows up the
 > substation (and maybe the East Coast power grid???? *grin*)
 > They're working on redundant/fail-safe clock distribution.
 > 
 > The thing has got a LOT of packet switching capability (more
 > than all the telephone switching capability in the world) to
 > get the processors to communicate.
 > 
 > An interesting and ambitious architecture!
 > 
 > 
 > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 > ~  Phil Koopman             5551 Beacon St.             ~

  I wanted to thank you for clearing up some of my misinformation.
This discussion start over someone mocking someone else about the plans
to build tera-machines. I cross posted into comp.arch hoping someone would
clear it up and someone did.

Oh, didn't the speaker say that the speed of the beast was going to be
up'ed to 3 teraflops?

BTW: 32000 processor sound about the right number considering what
was said about the switching network.  
-- 

Eddie Wyatt 				e-mail: edw at ius1.cs.cmu.edu