Make doesn't understand .SUFFIXES: .b .c .s .i .o

[jc at netrix.nac.dec.com]

This has bothered me for some time, and it sure seems that make oughta
know how to handle it, but it never does.  What  I've  been  doing  is
using  a  local preprocessor to convert foo.b to foo.c, where foo.b is
basically C with a bunch of extra stuff that cpp can't  handle.   I've
written a simple translator b-c and told make:
	.SUFFIXES: .b .c .s .i .o
	.b.c:   ;b-c 0-8t 9 <$*.b >$@
	.c.o:   ;cc -c $(CFLAGS) $*.c

The  b-c  params to make are irrelevant to this example; the annoyance
is that these three lines don't explain to make how to  convert  foo.b
to foo.o, as is shown by:
	% touch foo.b
	% make foo.o
	Make:  Don't know how to make foo.o.  Stop.

If I tell it to make foo.c, it works, and then it knows  how  to  make
foo.o  from  foo.c;  the problem is that it doesn't seem to understand
the .b -> .c -> .o sequence, although it appears to  be  explained  in
the  above.   But  this is a pain, because the clean:  entry of course
tosses out the .c files, and then the chain is broken.

What I've been doing is adding lines to the makefile like:
 foo.c:  foo.b
and then it works fine.  But this seems stupid; every time I add a new
source module, I have to add a line like this.  It is obvious that the
.SUFFIXES was intended to handle cases like this, but it doesn't.   So
why doesn't it?  I've dug around in TFM several times, to no avail...

Am I crazy for expecting this to work?  Does anyone  have  a  makefile
that does this successfully?