88K table walk

[Tom Armistead]

In article <415 at ncr-sd.SanDiego.NCR.COM> jml at ivory.SanDiego.NCR.COM (Michael Lodman) writes:
>According to Motorola, the 88200 CMMU does not cache the page and
>segment descriptors it fetches during a table walk. This would seem

    Wrong! The 88200 does cache page descriptors.  Up to 56 page descriptors
(each descriptor maps 4K of virtual space) can be cached in each CMMU.  The
page descriptor cache is managed by the CMMU.

    In addition, per CMMU, software can map up to eight 512K chunks of
memory via the block address translation cache and avoid table walks on
contiguous areas of memory (e.g. kernel text and data, i/o areas, etc.).
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