Make dependencies and nested include files

[Erik Baalbergen]

In article <10115 at encore.Encore.COM> corbin at maxzilla.UUCP () writes:
>
>Can this be done in make or is
>
>test.c:	    test.h test1.h test2.h
>
>the only way it will work.
In fact, it's
test.o:	test.h test1.h test2.h

>
>The problem with the second example is that I'm working on a product
>with hundreds of files and maintaining dependencies manuallly is tedious
>and error prone.  I would like to do automatic dependency generation.
Lots of "mkdep"s, "makedep"s, and "makedependencies"s are floating around in
the world.  There may be one on your system.
Some cc's are equiped with a "-M" option.  "cc -M f.c" then produces
make dependency lines in the right format.  (-M causes cpp to print out
the names of the files which are included.)

The "make-dependencies" or "cc -M" can then be used from within the Makefile:

-- start Makefile --
depend:
	sed '/^#THE FOLLOWING LINES ARE GENERATED/,$$d' Makefile > Makefile.new
	echo '#THE FOLLOWING LINES ARE GENERATED' >> Makefile.new
	$(MKDEP) $(CSRC) >> Makefile.new
	mv Makefile.new Makefile
#THE FOLLOWING LINES ARE GENERATED
# don't put any hand-written stuff here
-- end Makefile --

The command "make depend" will create a new Makefile with the dependencies 
appearing after the "#THE FOLLOWING LINES ARE GENERATED" line.

Erik Baalbergen (erikb at cs.vu.nl)
-- 
Erik H. Baalbergen				    <erikb at cs.vu.nl>
Vrije Universiteit / Dept. of Maths. & Comp. Sc.
De Boelelaan 1081
1081 HV Amsterdam / The Netherlands		tel. +31 20 548 8080