make(1) questions

[Conor P. Cahill]

pefv700 at perv.pe.utexas.edu writes:
>I have 2 executables that are "made" using the same sources files.  The only
>difference is that for one a cpp(1) macro is defined, for the other it is not.

The easiest way to do this is to create a new rule:

.c.p:
	if [ -s $*.o ]; then \
		mv $*.o sv.$*.o; \
	fi
	$(CC) -c $(CFLAGS) $(SPECIAL_CPP_FLAG) $<
	mv $*.o $*.p
	if [ -s sv.$*.o ]; then \
		mv sv.$*.o $*.o; \
	fi

and have the program that needs the define depend upon objects with a .p
extension.  if they are all the same sources you could do the following:

SRCS=name1.c name2.c ...

PGM1OBJS=$(SRCS:.c=.o)
PGM2OBJS=$(SRCS:.c=.p)

pgm1: $(PGM1OBJS)
	cc -o $@ $(PGM1OBJS)

pgm2: $(PGM2OBJS)
	cc -o $@ $(PGM2OBJS)

>Lastly, my home directory has a $ in it (thanks to an NFS mount to a VAX :-().
>I would like to do something like:

>$(PROG): object files...
>	cc -o $(PROG) options... object files... libs...

put single quotes around the $(PROG).  For example:

 	cc -o '$(PROG)' options... object files... libs...

Note that you should only do this for shell command lines.  Makefile
directives may get confused.

-- 
Conor P. Cahill            (703)430-9247        Virtual Technologies, Inc.
uunet!virtech!cpcahil                           46030 Manekin Plaza, Suite 160
                                                Sterling, VA 22170