Adaptec and DMA (long)

[Karl Denninger]

In article <1990Nov02.021739.9280 at ddsw1.MCS.COM> nvk at ddsw1.MCS.COM (Norman Kohn) writes:
>There have been many comments about boards that won't support
>the Adaptec 1542[AB] SCSI bus master controller.
>The board has a BIOS test routine, but I can say from experience
>that it's possible for a motherboard to pass this test and
>still generate errors running unix.  Timing and/or DMA problems
>on the motherboards have usually been blamed.  

Actually, it's usually the case that the motherboard fails to deassert
IOCHRDY (I think that's the name of the signal) which is supposed to cause
the adapter to immediately relinquish the bus.

>I spoke with another board vendor last night and got another interesting
>comment.  He claims that the problem lies in the 1542B, which
>allegedly sits on the bus too long during boot-up.
>He says that a bus master is responsible for releasing the bus in
>time for memory refresh, and that Adaptec's failure to release
>the bus in time causes memory loss with predictably random (but poor)
>results.  A fix may be ready RSN.  I have not discussed this yet
>with Adaptec.

Not true.  The motherboard is responsible for telling the adapter
when to shut the heck up and get off the bus if it has to do so.  That's
what IOCHRDY is all about.  The 1542x boards all get off immediately when
this signal so indicates.

Every board I've seen so far that had trouble with the 1542B didn't bother
indicating that it was time for refresh.... how is an adapter supposed to
divine what the timing requirements are for this?

Get out a scope and look at the appropriate pins on the bus.  You'll see
what I've seen many times before.

Part of the problem is that bus mastering isn't often used, and thus isn't
often tested by motherboard makers.  It IS getting more common for companies
to "care" about this these days... :-)


--
Karl Denninger	AC Nielsen
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(708) 317-3285
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