ISA bus limitations (Re: binary Mach distribution for 386)

[Thomas Hoberg]

In article <1991Jan16.185851.2419 at ico.isc.com>, rcd at ico.isc.com (Dick
Dunn) writes:
|> > You wouldn't think the ISA bus was so nifty if you were trying to do
|> > DMA over it (or use memory-mapped devices) on an ISA-bus machine with 
|> > over 16MB of memory on it...  
|> 
|> That's definitely a problem...although it really focuses on the DMA
|> controllers (wretched devices for various reasons) more than the I/O bus.
|> Somewhere along the way to moving memory off the ISA bus, someone should
|> have come up with a better DMA controller that also had a way to get to
|> more memory.
|> -- 
Nobody (but the floppy) really uses those wretched devices. These so called
bus mastering controllers just pull the DREQ lines to get the CPU off the bus.
The DMA they do themselves. But no DMA controller, however smart, can
circumvent the fact that there are only 24 address lines on the ISA bus.
|> Dick Dunn     rcd at ico.isc.com -or- ico!rcd       Boulder, CO   (303)449-2870
|>    ...Mr. Natural says, "Use the right tool for the job."
----
Thomas M. Hoberg   | UUCP: tmh at bigfoot.first.gmd.de  or  tmh%gmdtub at tub.UUCP
c/o GMD Berlin     |       ...!unido!tub!gmdtub!tmh (Europe) or
D-1000 Berlin 12   |       ...!unido!tub!tmh
Hardenbergplatz 2  |       ...!pyramid!tub!tmh (World)
Germany            | BITNET: tmh%DB0TUI6.BITNET at DB0TUI11 or
+49-30-254 99 160  |         tmh at tub.BITNET