New DEC announcement, 7/11

[Mark G. Johnson]

In article <18553 at mimsy.UUCP> steve at fnord.umiacs.umd.edu (Steven D. Miller) writes:
>   Here's the quick summary of what was announced:
>
>	3) DECserver 5810/DECserver 5820.  Features:
>		MIPS R3000 chipset, 18-20 MIPS per CPU, 2.1/4.8 MFLOPS
>		    LINPACK per CPU, 2 CPUs max; I suspect that plugging
>		    in more CPUs will work, but I also suspect that two
>		    saturate the XMI bus, and that's why DEC doesn't want
>		    to sell this with more than two CPUs
>		32-256MB memory (ECC)
>		BI bus as I/O bus
--------------------------------------------------------------------------
 
 When the R3000 processor takes a cache-miss, an entire "cache block"
 -- (1 to 32 words, boot-configured) -- is fetched from main memory.

 The CPU/cache can receive them at a rate of one word/cycle (4 bytes/40ns)
 or a bandwidth of 100 Megabytes/second.

 Could someone enlighten me?  What's the peak bandwidth of the "XMI bus"?
 Can it do >= 100 MBytes/sec?  Can it do N * 100MB/s  (for say N=1.3 in
 a 2-way multiprocessr)?   Thanks.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	...!decwrl!mips!mark	(408) 991-0208