DMA via 11/780 Unibus BDP.

[Peter Corke]

We have recently written a driver for an IEU-11, which is a Unibus dma 
IEEE-488 bus interface card produced by DEC's CSS group.  We are 
running 4.2BSD on an 11/780.  The driver accesses memory via a UBA BDP.

The IEEE-488 is a bytewide bus, so each dma memory access is for one byte.
The driver works fine for dma read, that is IEEE -> memory (DATOB cycles).
However, for writing, memory -> IEEE (DATI cycles), the data is scrambled
(in an 8 byte cyclic fashion (8 bytes is also the length of the BDP's 
buffer...)).

The Vax hardware handbook states that memory accesses via a BDP should
be word wide, and to consecutive increasing memory addresses.  
During write, memory->IEEE, the IEU-11 will perform pairs of DATI 
cycles to the same address as it reads the high and low byte of each word.
This violates the stated rules applying to BDP's.

My question is; is there anyway that a bytewide dma device can read from
memory via a BDP ?  If not, then boards like the IEU-11 can only perform 
inefficient memory access via a DDP.

The driver is now working using a DDP, though the data rate is noticeably
lower than the version using the BDP (which included a software kludge to
inversely prescramble the data).

				Peter Corke
-- 
Peter Corke, CSIRO Div of Manufacturing Technology, Melbourne, Australia.

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