UNIVS: Unix for J-11 or 11/84

Joseph S. D. Yao jsdy at hadron.UUCP
Thu Apr 17 16:43:34 AEST 1986


In article <6858 at boring.UUCP> jack at mcvax.UUCP (Jack Jansen) writes:
>In article <6552 at utzoo.UUCP> henry at utzoo.UUCP writes:
>> [Replying to an article asking how to configure V7 for a J-11]
>>Long odds you will find that the thing acts pretty much like a 70 as far
>>as Unix is concerned.  ...
>Quite right, but the gotcha is in the 'couple of small changes'.
> ...
>Something else: If my memory serves me right, a J-11 doesn't have
>separate I/D.

That last is incorrect.  The latest (1985/6) Processor Handbook
has a table of comparisons.  This table must be verified on each
point:  e.g., the table says that the clock register is inaccessible,
and the Handbook text says that it is accessible.  For details, one
must now consult a companion volume, the PDP-11 Architecture Handbook.
Is DEC deciding to make more money in the publishing business?

Per the table (70 vs 84, w/ 73-A and -B where different from 84):
84 has built-in FPP instrs, and MFPT (Move from Processor Type -> 5),
MTPS (Move To Processor Status), MFPS (Move From Processor Status),
and CSM (Call to Supervisor Mode) instructions.  Per the table, the
11/70 and 11/84 can take a KE11A or KE11B to add mul, div, and shift,
while the 11/73 (Q-bus) can't.

In kernel mode, one has the option of an illegal instruction trap
when the 84 executes HALT.  Of course, you never get an FPP ILLINT.
Register and PC value on trap are not always what the 11/70 expects:
this impacts restarts after interrupt.

On the 70, power failure interrupts an INIT signal (RESTART).  The
84 and 70 have different durations anyway.

The 70 and 84 can have 3840 Kb; the 73's, 4088.  The 73's and 84
are the only ones to interpret PSW mode 10 as user; all others
are unpredictable.  84 has no MMR0 bits 8 (maint) and 12 (MMU
trap), MMR2 doesn't trap int vectors, MMR3 bit 3 (ENABLE) (?)
exists and functions.  PAR can't be program memory; bits 0 and 7
(trap any access) don't work.  Memory bus differs.  Bus timeout
									        differs, of course.

I'm only half way through the table ... get a copy from DEC,
and read the rest.  If you live in Antarctica, drop me a line.
-- 

	Joe Yao		hadron!jsdy at seismo.{CSS.GOV,ARPA,UUCP}



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