When did paging get into System V

[Chris Torek]

In article <7886 at brl-smoke.ARPA> gwyn at brl-smoke.ARPA (Doug Gwyn ) writes:
>Okay, if that is the case then it still supports the point I was making,
>which is that the 4BSD virtual memory scheme was quite heavily tied to
>the VAX design.  Apparently the Sun(-1) MMU provided enough hooks for a
>VAX emulation to work, but other vendors of super-mini class machines
>have not always found this to be the case for their MMUs (at least not
>without unacceptable performance penalties, e.g. overly-large reference-
>bit tables).

??  The Sun-1 ran a swapping kernel.  At least, the old Sun 1 box (now
holding a Sun 2 CPU, and now known as burble.cs.umd.edu) ran a V7ish
system when we first got it.

Reference bit tables?

Note also that the Berkeley Tahoe port elides the reference bit
simulation, using the real reference bit in the Harris/CCI/Sperry
PTEs.  The work to do that consisted mainly of disabling a few dozen
lines of code with `#if vax'.  The Tahoe is a virtual address cache
machine, too (although it has an `uncache' bit in each PTE, which makes
I/O easier).

>DMR mentioned to me not too long ago that the Bell Labs research folks
>had also thought that replacing the 4BSD memory management scheme in
>their system (which evolved from an early Berkeley VAX release) would
>be worth doing, just that they hadn't found the time.

Even Berkeley thinks so.  The code *is* overly Vax-oriented, and is
old and creaky and rather messy.  But it still matches a large number
of real machines.  If you have a two-level page table and PTEs, the
4BSD VM code will probably work with only semi-major tweaking :-) .
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163)
Domain:	chris at mimsy.umd.edu	Path:	uunet!mimsy!chris