Make:defining macros with filenames that have '$' in them

[Conor P. Cahill]

In article <27177 at cup.portal.com> DeadHead at cup.portal.com (Bruce M Ong) writes:
>I have to include a file with '$' in its name (i.e. abc.$cf) in
>a macro definition in Make. For the life of me I couldnt figureout how to 
>escape that specific '$' sign in the make file so make wont try to expand
>abc.$cf into "abc.f"
>
>How can I do this? Any hints from ya gurus will be appreciated!

This all depends upon how you want to use it. 

If you just want to have the $ appear in the macro you can escape the
$ by preceding it with another $.  For example:

TEMP=$$tmp

However, if you want to use this in a command line like:

	echo $(TEMP)

you must also escape the dollar sign for the shell.  This can be done by 

TEMP=\$$tmp
	echo $(TEMP)

or

TEMP=$$tmp
	echo \$(TEMP)


If what you are referring to is the inference rules you can do something
like the following:

	.SUFFIXES:	.$$a .a
	.$$a.a:
		cp '$*.$$a' $@
	
	test.a:

Which will copy test.$a to test.a in the current directory if test.$a is
newer than test.a.

Good luck
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