PC/AT HD controller device driver code

[Emmett Lazich]

I have some questions concerning SCO's hard disk driver
code.  Maybe someone at SCO would care to reply?  :-)


I am interested in finding out what goes on when a standard hard disk
controller is being used.  (eg.  WD1003-WA2) By "what goes on", I
meant questions such as the following: (assume we are doing a read
operation)

1) Does the processor do a rep insw or is DMA used?  I have heard
about the 8237's programmed mode which does not require DREQ/DACK,
but can it be (or is it) used?

2) Assuming the processor transfers the sectors: Is a sleep() called
inbetween sectors so that some task time processing can occur?
(NB: I wrote a serial device driver that interupted at spl5 and chars
were still echoed striaght away)

3) Assuming rep insw once again: What is the system priority level
while reading the sector buffer?  In particular, could slp7 serial
interupts cause a drive with a low interleave to have do an extra
revolution because the cpu was too busy.


Once the above questions are answered I would like to be able to
answer these  questions concerneing performance.

a) If task time processing is attempted inbetween sector transfers.
Then how does one determine the ideal interleave for their system?
For example: If a system's thoroughput is mainly governed by disk i/o
time, then would a low interleave be best (ie 2:1) even though all
that would get done (a guess here!) is a context switch to task time
processing and then one straight back again, with little or no
effective processing accomplished in doing so.

BTW: if DMA is used, the situation is very different.  But still, if
someone would care to explain to me what goes on in that case, I
would appreciate it.

b) Are PC/AT RLL controllers the same as the MFM type as far as
register functions are concerned?  I mean, if the code that "talks"
to the controller can deal with different numbers of sectors per
track, then will the same code work with either controller?  Well....
I'll be more specific.  If we purchased a DTC 16 bit RLL controller,
would it work with Xenix 2.2.1 on a 10 MHz 1 ws 80286 with a 2:1
interleave? :-)

c) Considering DMA, sleep() calls, RLL and everything i've mentioned
so far. What would happen with a 1:1 interleave?

d) Finally there's ESDI controllers.  I know that communication is
done differently between the controller and the drive.  But what are
they like for the programmer who writes the device driver code to use
them? Do they offer the same familiar registers of the WD1003-WA2 or
are they totally different? What about DREQ?DACK lines ?


------

Any answers or additional information greatly appreciated.
Thanks!

---

-----------------------------------------------
Internet: emmett at runx.ips.oz.au		JANET:  runx.oz!emmett at ukc
UUCP: uunet!runx.ips.oz.au!emmett	ARPA:	emmett%runx.oz at seismo.css.gov