minimizing winchester disk access time

[R.TRAUBEN]

I am interested in improving my disk sub-system from an overall
systems point of view. Clearly there are a number of factors 
which come into play. Some are stricly mechanical, some are 
hardware configuration dependent, and the balance are OS software
stategy dependent.

I am interested in getting pointers to any books or articles
which deal with these issues. Magazines and nety articles are
not acceptable since the gloss/content ratio is too high.
Can some one help me out?


PURE MECHANICAL DISK CHARACTERISTICS are:

- rotational latency, 
- seek time (1/3 radius travel time)

HARDWARE CONFIGURATION CHARACTERISTICS are:

- drive to controller data transfer rate (ST506, ST412HP, ESDI, SMD),
- number of drives tied to the controller (drive bus contention & overruns),
- existence semiconductor memory buffer/cacheon the controller itself,
- any intelligence (policies in processor) added the controller to make 
  dynamic track swapping, out-of-order sector transfers, out-of-chronological
  order disk request scheduling to mitigate seek times, prefetch behind,
  postfetch slightly ahead, read entire track - and defer service to any
  stacked prior seek request)
- size of said buffers/cache
- existence of main memory buffers (sys. buffer cache) outside of the
  controller board itself.
- the width and peak transfer rate of the disk controller to main memory
  data transfer bus.
- the peak transfer rate of the DMA controller to main memory transfer rate,
- the overhead in bus arbitration policy being used by the DMA controller. 
  (request-grant-transfer 1 word- release bus) or (request-grant- transfer
  entire sector then release bus).
- number of busses and controllers between the drive itself and main memory
  (ST506, IPI, SCSI, VMEBUS, VMXBUS)
- other stuff ...

SOFTWARE CONFIGURATION CHARACTERISTICS are:

- main memory size
- page size,
- page reference policy (R&M update policy in MMU)
- overhead in setting up and tearing down the DMA transfer,
- presence of system buffer cache,
- whether 1 or 2 DMA jobs are necessary to make the blocked process runnable,
  (controller to user space, or controller to system buffer cache to user
   space)
- adaptive prioritization of seek request based on length of wait interval,
- other stuff ...


In particular, I am interested in finding out about any published studies
or unpublished personal experiences which attempted to determine which
of the above get a good "return on investment" and which ones are noise.

The configuration I am most interested in studying is the general purpose 
mini/micro market, at cost less than $100K, with 1-2 Mega bytes main store,
100 Mbyte disk with 35 ms. 


Send pointers to ../inhp4/houxk/rdt.

Thank you,

Richard Trauben
AT&T Bell Labs