WD2010 / No ECC

[was-John McMillan]

In article <15462 at rphroy.UUCP> tkacik at rphroy.UUCP (Tom Tkacik) writes:
:
>
>I installed the WD2010 into a standard 7300, and can verify that it makes
>the disk drive work better.  After installing Lenny's errnotify(1) command,
>I have been seeing at least 3 or 4 disk errors a day.  If I was doing
>anything, it would go up.  Compiling gcc could generate about 20 or 30
>errors.
:
>It must be the error correction circuitry.  I recommend the change
>even if you are not using a big disk.  (Who knows, maybe someday you will. :-))
:

Several people have made assertions about installing the WD2010:
	1) It has (a) reduced errors, or (b) recovered 'lost' disks;
	2) It must be the Error Correcting Code [ECC] that does this.

I don't dispute (1) and am happy this chip helps.  We all need
	a break once in awhile ];-)

However, these references to ECC are fanciful or an incorrect
	use of the term.

THERE IS an ECC generator/checker on the WD2010.  (Its use is
	indicated/triggered by SDH reg bit7=1.) Since the kernel
	was designed to support the WD1010 chip -- which lacks ECC --
	there is NO kernel support of ECC.  

The WD1010/WD2010's CRC mode appends a 2 byte field to the end of
	each data field.  The ECC mode appends a 4 byte field.
	Without having tried it, two disk formats seem incompatible,
	requiring a re-format when changing between CRC and ECC.
	It would be nice were the ECC supported -- but I've never
	even identified a way to figure out WHICH chip is plugged in:
		a) W.D. technical support said THEY had no idea of
			how to figure this out.
		b) Perhaps some specific ECC associated command to
			a WD1010 would fail identifiably, but it
			wasn't obvious at a glance.
 
Since IT AIN'T THE ECC, wherein lies the magic of the WD2010?
	Without getting into the theory of how a Phase Lock Loop [PLL]
	works -- which would be ridiculous for ME to try 8) -- let's
	just assert a smarter PLL circuit makes fewer errors in
	assessing marginal signals.  Ie: As the waveforms vary
	from an "ideal" model, the poorer circuit will begin to
	mis-assign transitions and mis-track the signal.

PLL circuits are NOT ECC, they are just a tracking mechanism meant
	to deal with normal perturbations and PREVENT errors by
	constant small adjustments to timing calculations.

So... ECC's OUT, the PLL's a guess, and why in honk am I here today?

john mcmillan	-- att!mtunb!jcm