volatile isn't necessary, but it's there

[John Woods, Software]

In article <144 at obie.UUCP>, wes at obie.UUCP (Barnacle Wes) writes:
> In article <48767 at sun.uucp>, guy at gorodish.Sun.COM (Guy Harris) writes:
> | It is worth noting, for example, that there is no guarantee that "++mutex"
> | is an atomic operation.
> Another good reason NOT to use a SPARC for anything other than a
> paperweight.  On a reasonable processor like the M68000, `++mutex'
> becomes an atomic operation like `addq	#1,mutex'.
> 
Bad news.  "addq #1,mutex" is NOT atomic on an MC68000 processor, reasonable
or not.  If you have a multiprocessor, it is easy for another processor to
sneak in between the read bus cycle and the write bus cycle and drop another
value into mutex (it may lose, but it will think it won).  That is why the
68000 has the TAS instruction; TAS does NOT release the bus between the
read and the write cycle.

I would be interested to know how one does multi-processor locking on a
SPARC, however (or other RISC processors).  Anyone who *knows* care to
comment?

--
John Woods, Charles River Data Systems, Framingham MA, (617) 626-1101
...!decvax!frog!john, ...!mit-eddie!jfw, jfw at eddie.mit.edu

"Take Greg Nowak.  He's divisible by 59."	- Not Matt Crawford