volatile isn't necessary, but it's there

[Tim Olson]

In article <2182 at frog.UUCP> john at frog.UUCP (John Woods, Software) writes:
| In article <144 at obie.UUCP>, wes at obie.UUCP (Barnacle Wes) writes:
| I would be interested to know how one does multi-processor locking on a
| SPARC, however (or other RISC processors).  Anyone who *knows* care to
| comment?

The Am29000 has a "loadset" instruction, which loads a register from a
memory location, then sets that memory location to all-ones.  This
sequence is non-interruptable, and the *LOCK pin is asserted throughout
the entire transaction.

	-- Tim Olson
	Advanced Micro Devices
	(tim at amdcad.amd.com)