J11 chipset revisited (bug fixed)
Stephen C. Woods
scw at cepu.UUCP
Sat Nov 3 05:18:27 AEST 1984
OOPS I goofed, In the previous release I inadvertantly left an
instruction out of the dma tests. The missing instruction was a
cfcc (Copy Floating Condition Codes). This bug causes the dma
tests to ALWAYS fail (even on good chips). Following this is a
posting of the entire (Corrected) article.
I am *VERY* sorry if my mistake caused anyone any problems.
The code in the diagnostics has been checked against the listing in the
letter from DEC (Nov 2,1984).
I'd like to thank Paul McKenney (mckenney at orstcs.UUCP) for pointing
the problem out to me.
--------------------------begin updated notice-----------------------------
This is extracted from a notice dated 8-Aug-1984, from the DEC
Microcomponents Group.
DEC has discovered a problem with ~9% of the data chips on the
DCJ11-AC/KDJ11-AA boards. The problem only affects chips with date
codes prior to and including 8419 (1984, 19th week). If you don't have
an 11/73 just drop the rest of this (unless you're interested).
The problem is a sensitivity to specific integer data values in
additon or subtraction simultaneously with cache miss or dma transfer.
A similar problem occurs with Double Floating point operations, but only with
DMA activity.
The problem is most pronounced under worst case voltage (high) and temperature
(high) conditions.
If you have a doubtful date code (<= 8419) then you should run the tests at the
end of this article under the worst case conditions.
"... A ''hot line' has been established to answer any questions that may arise
and to explain the return policy for affected devices. The hot line
number is (617)-497-7765. ..."
To identify your date code use the following diagram (Very rough aproximation).
top of board (component side up)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|| || || || |
|| || || || |
d4 d3 d2 d1 |
|
60 31 |
---------------------------- |
| ------ ------ | |
| |ctrl| DCJ11-AC | |<-|--- data chip
| |chip| |84xx|<-|--------Date code
| ------ ------ | |
---------------------------- |
1 30 |
=== w9 |
w8 === |
=== w7 |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--- -|
----| | |
| | |
| | |
---------------- ----------------------
-----------------------------------cut here-------------------------------------
Program 1 tests J11 integer data sensitivity. put in with ODT, starts at 1000
a halt at 1046 means that you have the problem.
.TITLE J11 NON DMA TEST
000000 .ASECT
177566 XBUF=177566
.EVEN
000004 .=4
address value code
000004 000006 .WORD 6
000006 000000 .WORD 0
000010 000012 .WORD 12
000012 000000 .WORD 0
000244 .=244
000244 000246 .WORD 246 ;FPP TRAP
000246 000000 .WORD 0
001000 .=1000
001000 BEGIN::
001000 012706 MOV #1000,SP
001000
001004 106427 MTPS #340 ;INTERUPTS OFF
000340
001010 012737 MOV #415,@#177746 ;INHIBIT CACHE
000415
177746
001016 START:
001016 012700 MOV #-1,R0 ;SET UP R0
177777
001022 012701 MOV #33677,R1 ;FIRST OPERAND
033677
001026 012704 MOV #2000,R4 ;SECOND OPERAND
002000
001032 101$:
001032 010402 MOV R4,R2 ;INITALIZE
001034 060000 ADD R0,R0 ;FIRST ADD (NEVER FAILS)
001036 060102 ADD R1,R2 ;THIS MIGHT FAIL
001040 020227 CMP R2,#35677 ;DID IT?
035677
001044 001401 BEQ .+4 ;BIF OK
001046 000000 HALT ;USUALL FALURE R2 = 75677
001050 005200 INC R0 ;MAKE R0 EQUAL TO -1 AGAIN
001052 112737 MOVB #120,@#XBUF ;WRITE ASCII 'P' TO CONSOLE
000120
177566
001060 000764 BR 101$ ;AND AGAIN
001000 .END BEGIN
---------------------------test 2--------------------------------------------
for testing with rx02 (both integer and Fpp tests).
Uses fill buf (needs no media in drive).
load with ODT, starts at 1000.
.TITLE J11 DMA TEST (RX02)
;
; THERE ARE 3 HALTS
; 1120 J11 FAILURE (CALL DEC)
; 1164 J11 FAILURE (CALL DEC)
; 1210 RX FAILURE
;
000000 .ASECT
000000 AC0 = %0
000001 AC1 = %1
000002 AC2 = %2
000003 AC3 = %3
000004 AC4 = %4
000005 AC5 = %5
000006 AC6 = %6
000007 AC7 = %7
177170 RXCSR = 177170
177172 RXDB = 177172
177566 XBUF = 177566
.EVEN
000004 . = 4
address value opcode
000004 000006 .WORD 6
000006 000000 .WORD 0
000010 000012 .WORD 12
000012 000000 .WORD 0
000244 . = 244
000244 000246 .WORD 246 ;FPP TRAP
000246 000000 .WORD 0
001000 . = 1000
001000 BEGIN::
001000 012706 MOV #1000,SP ;SET UP STACK
001000
001004 000237 SPL 7 ;INTERUPTS OFF
001006 000005 RESET
001010 012737 MOV #400,@#177746 ;ENABLE CACHE
000400
177746
001016 START:
001016 012703 MOV #RECANS,R3 ;ERROR BUFFER
002060
001022 012702 MOV #RESLT1,R2 ;UPPER WORD RESULT
002020
001026 012704 MOV #DATS1,R4 ;UPPER WORD DATA
002000
001032 004737 JSR PC,@#FLTADD ;DO FPP TEST (WORST CASE)
001066
001036 012704 MOV #DATS2,R4 ;UPPER WORD DATA
002030
001042 012702 MOV #RESLT2,R2 ;UPPER WORD RESULT
002050
001046 004737 JSR PC,@#FLTADD ;THE OTHER CASE
001066
001052 004737 JSR PC,@#LOWER ;INTEGER TEST
001126
001056 112737 MOVB #'P,@#XBUF ;PRINT END OF PASS MARKER
000120
177566
001064 000754 BR START ;AND DO IT AGAIN
001066 FLTADD:
001066 012705 MOV #77,R5 ;LOOPING COUNT
000077
001072 170127 LDFPS #7700 ;SET TO DOUBLE PRECISION
007700
001076 004737 JSR PC,@#RXSERV ;STARTUP DMA
001174
001102 101$:
001102 010401 MOV R4,R1 ;POINT TO TEST DATA
001104 172421 LDD (R1)+,AC0 ;FIRST OPERAND
001106 172021 ADDD (R1)+,AC0 ;TRY ERROR CAUSING OPERATION
001110 173412 CMPD (R2),AC0 ;TEST IT
001112 170000 CFCC ;GET STATUS FROM FPP TO STATUS (WAS MISSING)
001114 001402 BEQ 102$
001116 174013 STD AC0,(R3) ;ERROR
001120 000000 HALT ;2060-2066 HAS BAD
001122 102$:
001122 077511 SOB R5,101$ ;LOOP
001124 000207 RTS PC ;AND GO BACK
001126 LOWER:
001126 012705 MOV #77,R5 ;LOOP COUNT
000077
001132 014100 MOV -(R1),R0 ;LOAD -1 TO R0
001134 012701 MOV #33677,R1 ;FIRST OPERAND
033677
001140 012704 MOV #2000,R4 ;SECOND OPERAND
002000
001144 004737 JSR PC,@#RXSERV
001174
001150 150$:
001150 010402 MOV R4,R2 ;INITALIZE
001152 060000 ADD R0,R0 ;FIRST ADD (NEVER FAILS)
001154 060102 ADD R1,R2 ;THIS MIGHT FAIL
001156 020227 CMP R2,#35677 ;DID IT?
035677
001162 001401 BEQ 152$ ;BIF OK
001164 000000 HALT ;USUALL FALURE R2 = 75677
001166 152$:
001166 005200 INC R0 ;MAKE R0 EQUAL TO -1 AGAIN
001170 077511 SOB R5,150$ ;AND AGAIN
001172 000207 RTS PC ;BYE
;*********************************************************
; LOAD 177(8) WORDS (DMA) FROM RXDATA
;*********************************************************
001174 RXSERV:
001174 105737 TSTB @#RXCSR ;CHECK FOR ERRORS
177170
001200 100004 BPL 5$ ;BIF OK
001202 013737 MOV @#RXDB,@#500 ;SAVE AT 500
177172
000500
001210 000000 HALT ;SORRY, TRY ANOTHER PACK
001212 032737 5$: BIT #40,@#RXCSR ;CONTROLER READY?
000040
177170
001220 001774 BEQ 5$
001222 012737 MOV #401,@#RXCSR ;FILL BUFFER,(INTR OFF)
000401
177170
001230 105737 10$: TSTB @#RXCSR ;TR READY?
177170
001234 100375 BPL 10$ ;WAIT FOR IT
001236 012737 MOV #177,@#RXDB ;LOAD WC
000177
177172
001244 105737 20$: TSTB @#RXCSR ;TR READY?
177170
001250 100375 BPL 20$ ;WAIT FOR IT
001252 012737 MOV #RXDATA,@#RXDB ;SET XFER ADDRESS
004000
177172
001260 000207 RTS PC ;AND GOBACK
002000 . = 2000
002000 DATS1:
002000 040267 .WORD 40267,-1,-1,-1 ;UPPER WORD
002002 177777
002004 177777
002006 177777
002010 040204 .WORD 40204,0,-1,-1
002012 000000
002014 177777
002016 177777
002020 RESLT1: ;EXPECTED RESULT
002020 040436 .WORD 40436,0,77777,-1
002022 000000
002024 077777
002026 177777
002030 DATS2: ;LOWER WORD
002030 040377 .WORD 40377,173777,-1,-1
002032 173777
002034 177777
002036 177777
002040 040200 .WORD 40200,2000,-1,-1
002042 002000
002044 177777
002046 177777
002050 RESLT2: ;EXPECTED RESULT 2
002050 040477 .WORD 40477,177000,77777,-1
002052 177000
002054 077777
002056 177777
002060 . = 2060
002060 RECANS:
002060 .BLKW 4 ;ERROR VALUE HERE
004000 . = 4000
004000 RXDATA:
004000 .BLKW 5000. ;DMA SPACE
001000 .END BEGIN
---------------------------test 3-----------------------------------------
Same as test 2 but uses RL02/1 (needs a pack) to read from.
load with ODT, starts at 1000.
; DON'T FORGET TO WRITE PROTECT THE PACK
; THERE ARE 3 HALTS
; 1134 J11 FAILURE (CALL DEC)
; 1200 J11 FAILURE (CALL DEC)
; 1216 RL FAILURE, TRY A DIFFERENT PACK
;
000000 AC0 = %0
000001 AC1 = %1
000002 AC2 = %2
000003 AC3 = %3
000004 AC4 = %4
000005 AC5 = %5
000006 AC6 = %6
000007 AC7 = %7
174400 RLCSR = 174400
174402 RLBA = 174402
174404 RLDA = 174404
174406 RLWC = 174406
177566 XBUF = 177566
.EVEN
000004 . = 4
000004 000006 .WORD 6
000006 000000 .WORD 0
000010 000012 .WORD 12
000012 000000 .WORD 0
000244 . = 244
000244 000246 .WORD 246 ;FPP TRAP
000246 000000 .WORD 0
001000 . = 1000
001000 BEGIN::
001000 012706 MOV #1000,SP ;SET UP STACK
001000
001004 000237 SPL 7 ;INTERUPTS OFF
001006 000005 RESET
001010 012737 MOV #13,@#RLDA ;RESET RL
000013
174404
001016 012737 MOV #4,@#RLCSR ;DO IT
000004
174400
001024 012737 MOV #400,@#177746 ;ENABLE CACHE
000400
177746
001032 START:
001032 012703 MOV #RECANS,R3 ;ERROR BUFFER
002060
001036 012702 MOV #RESLT1,R2 ;UPPER WORD RESULT
002020
001042 012704 MOV #DATS1,R4 ;UPPER WORD DATA
002000
001046 004737 JSR PC,@#FLTADD ;DO FPP TEST (WORST CASE)
001102
001052 012704 MOV #DATS2,R4 ;UPPER WORD DATA
002030
001056 012702 MOV #RESLT2,R2 ;UPPER WORD RESULT
002050
001062 004737 JSR PC,@#FLTADD ;THE OTHER CASE
001102
001066 004737 JSR PC,@#LOWER ;INTEGER TEST
001142
001072 112737 MOVB #'P,@#XBUF ;PRINT END OF PASS MARKER
000120
177566
001100 000754 BR START ;AND DO IT AGAIN
001102 FLTADD:
001102 012705 MOV #500,R5 ;LOOPING COUNT
000500
001106 170127 LDFPS #7700 ;SET TO DOUBLE PRECISION
007700
001112 004737 JSR PC,@#RLSTRT ;STARTUP DMA
001210
001116 101$:
001116 010401 MOV R4,R1 ;POINT TO TEST DATA
001120 172421 LDD (R1)+,AC0 ;FIRST OPERAND
001122 172021 ADDD (R1)+,AC0 ;TRY ERROR CAUSING OPERATION
001124 173412 CMPD (R2),AC0 ;TEST IT
001126 170000 CFCC ;GET STATUS FROM FPP TO STATUS (WAS MISSING)
001130 001402 BEQ 102$
001132 174013 STD AC0,(R3) ;ERROR
001134 000000 HALT ;2060-2066 HAS BAD
001136 102$:
001136 077511 SOB R5,101$ ;LOOP
001140 000207 RTS PC ;AND GO BACK
001142 LOWER:
001142 012705 MOV #500,R5 ;LOOP COUNT
000500
001146 014100 MOV -(R1),R0 ;LOAD -1 TO R0
001150 012701 MOV #33677,R1 ;FIRST OPERAND
033677
001154 012704 MOV #2000,R4 ;SECOND OPERAND
002000
001160 004737 JSR PC,@#RLSTRT
001210
001164 150$:
001164 010402 MOV R4,R2 ;INITALIZE
001166 060000 ADD R0,R0 ;FIRST ADD (NEVER FAILS)
001170 060102 ADD R1,R2 ;THIS MIGHT FAIL
001172 020227 CMP R2,#35677 ;DID IT?
035677
001176 001401 BEQ 152$ ;BIF OK
001200 000000 HALT ;USUALL FALURE R2 = 75677
001202 152$:
001202 005200 INC R0 ;MAKE R0 EQUAL TO -1 AGAIN
001204 077511 SOB R5,150$ ;AND AGAIN
001206 000207 RTS PC ;BYE
;*********************************************************
; READ 5000(10) WORDS INTO RLDATA
;*********************************************************
001210 RLSTRT:
001210 005737 TST @#RLCSR ;CHECK FOR ERRORS
174400
001214 100001 BPL 10$ ;BIF OK
001216 000000 HALT ;SORRY, TRY ANOTHER PACK
001220 012737 10$: MOV #13,@#RLDA
000013
174404
001226 012737 MOV #4,@#RLCSR ;RESET IT
000004
174400
001234 132737 11$: BITB #1,@#RLCSR ;READY?
000001
174400
001242 001774 BEQ 11$ ;WAIT FOR IT
001244 105737 12$: TSTB @#RLCSR
174400
001250 100375 BPL 12$ ;DONE SET?
001252 012737 MOV #RLDATA,@#RLBA ;SET XFER ADDRESS
004000
174402
001260 005037 CLR @#RLDA ;SET FOR ZERO
174404
001264 012737 MOV #-5000.,@#RLWC ;5000 WORDS
166170
174406
001272 012737 MOV #16,@#RLCSR ;READ IT
000016
174400
001300 000207 RTS PC ;AND GOBACK
002000 . = 2000
002000 DATS1:
002000 040267 .WORD 40267,-1,-1,-1 ;UPPER WORD
002002 177777
002004 177777
002006 177777
002010 040204 .WORD 40204,0,-1,-1
002012 000000
002014 177777
002016 177777
002020 RESLT1: ;EXPECTED RESULT
002020 040436 .WORD 40436,0,77777,-1
002022 000000
002024 077777
002026 177777
002030 DATS2: ;LOWER WORD
002030 040377 .WORD 40377,173777,-1,-1
002032 173777
002034 177777
002036 177777
002040 040200 .WORD 40200,2000,-1,-1
002042 002000
002044 177777
002046 177777
002050 RESLT2: ;EXPECTED RESULT 2
002050 040477 .WORD 40477,177000,77777,-1
002052 177000
002054 077777
002056 177777
002060 . = 2060
002060 RECANS:
002060 .BLKW 4 ;ERROR VALUE HERE
004000 . = 4000
004000 RLDATA:
004000 .BLKW 5000. ;DMA SPACE
001000 .END BEGIN
--
Stephen C. Woods (VA Wadsworth Med Ctr./UCLA Dept. of Neurology)
uucp: { {ihnp4, uiucdcs}!bradley, hao, trwrb}!cepu!scw
ARPA: cepu!scw at ucla-cs location: N 34 3' 9.1" W 118 27' 4.3"
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