Help catching floating point exceptions

[sdl]

In article <91149.150333AER7101 at TECHNION.BITNET> AER7101 at TECHNION.BITNET (Zvika Bar-Deroma) writes:


Zvika> I've been told by my IBM rep.  that as IEEE didn't require that division
Zvika> by zero  be trapped and  signalled, then (some/many/most)  RISC machines
Zvika> don't, and he thinks, that unless  there's such a requirement from IEEE,
Zvika> they won't also in the forseeable future.

Your rep. is correct.  From IEEE 854-1987:  "There are five types of
exceptions that shall be signaled when detected.  The signal entails
setting a status flag, taking a trap, or possibly doing both".
Moreover, IEEE requires that if you implement IEEE trapping, that
"A trap handler should have the capabilities of a subroutine that can
return a value to be used in lieu of the exceptional operation's
results."  In the case of invalid operation and divide by zero
exceptions, the signal handler must be delivered the operand values
of the operation.  However, in the RISC System/6000's pipelined mode,
the floating point processor will have already destroyed the
operands by the time the branch processor can take the branch to
the trap handler.  Thus, it can only generate IEEE floating point
traps in sychronous execution mode.

Usual Disclaimer:  I write code, not make policy.

















--
--------------------------------------------------------------------
Stephen Linam   PSP Austin   T/L: 793-3674  Bell-net: (512) 823-3674
IBM Internet: sdl at adagio.austin.ibm.com        VNET: LINAM at AUSTIN
>From outside IBM:  sdl at glasnost.austin.ibm.com