88K table walk

[Tim Olson]

In article <1583 at nud.UUCP> tom at nud.UUCP (Tom Armistead) writes:
| In article <415 at ncr-sd.SanDiego.NCR.COM> jml at ivory.SanDiego.NCR.COM (Michael Lodman) writes:
| >According to Motorola, the 88200 CMMU does not cache the page and
| >segment descriptors it fetches during a table walk. This would seem
| 
|     Wrong! The 88200 does cache page descriptors.  Up to 56 page descriptors
| (each descriptor maps 4K of virtual space) can be cached in each CMMU.  The
| page descriptor cache is managed by the CMMU.

Yes, the translation is cached in the TLB entries, but I think the
question was do the memory accesses that are performed during the table
walk also get cached in the data cache? Or must they always go to main
memory? 


	-- Tim Olson
	Advanced Micro Devices
	(tim at crackle.amd.com)