Cache controllers, can Xenix use them?

[Mark Levy]

In article <195 at icc.UUCP>, wdm at icc.UUCP (Bill Mulert) writes:
# There are now a number of high performance 80386 motherboards in
# use in personal computers. Some of these machines have the Intel
# cache controller chip, and 32 to 64k of 30ns ram. Cacheing software
# for MsDos is available for those users.            ^^^^^^^^^^^^^^^^
                                                 THe caching software is
                                             disk-caching.  To the best of
                                             my knowledge, this is the only 
                                             type available

# My question is, is this cache controller usaeble by any of the
# Unix - Xenix kernels? Does'nt the kernel have to know about it
# in order to use it? Do any of Microport, SCO, Interactive
# support the chip? Would one be wasting ones money to buy a
# machine with a cache controller that would be running Xenix?

   There is a general misconception in the computing public, which is divided
into two groups... People who have worked on large systems, and those who 
haven't.  Those who haven't mistake software disk-caching for the kind of 
cache provided in hardware (and this isn't helped by software companies'
advertisements).  The typical disk cache reserves a portion of memory (not
the cache memory found on the motherboard) to store more than just the requested
information from the disk.  Since DRAM is much faster than the fastest ESDI
drives available, this serves to speed disk access.
   The hardware cache provided by manufacturers is memory cache.  It serves 
to speed up the access of main memory.  This allows very fast processors to 
use slower DRAM without having to add wait-states.

   According to SCO, the XENIX kernal is able to take advantage of the on-
board cache.  I am no 386 guru, but I imagine that the hardware would make
the use of the cache transparent to the system software.  (Please note: I got
the information from an SCO sales rep)

   For a terrific explanation of cache, see this month's BYTE magazine.
-- 
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Mark Levy { mhlevy at sbccvm.BITNET   } 	%       DISCLAIMER??? HA!!!  	
          { mhlevy at sbee.sunysb.edu }    % I admit it!  Go ahead, blame me,
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