Cache controllers, can Xenix use them?

[was-John McMillan]

In article <2727 at spdcc.SPDCC.COM> dyer at ursa-major.spdcc.COM (Steve Dyer) writes:
>In article <195 at icc.UUCP> wdm at icc.UUCP (Bill Mulert) writes:
>>There are now a number of high performance 80386 motherboards in
>>use in personal computers. Some of these machines have the Intel
>>cache controller chip, and 32 to 64k of 30ns ram.

	Sounds good.

>>						     Cacheing software
>>for MsDos is available for those users. 
	
	Sounds possible... maybe improbable, but possible.

>>My question is, is this cache controller usaeble by any of the
>>Unix - Xenix kernels? Does'nt the kernel have to know about it
>>in order to use it?

	Sanity still prevails....

>OK.  That would almost always be a BIOS issue, really.  A reasonable
>machine powers up cache enabled, with some keyboard strokes to manipulate
>cache on/off or and perhaps the speed of the machine.   Once XENIX or
>UNIX is running, it needn't touch this (and once it's running you can't
>use the BIOS keystroke method of manipulating it because the BIOS isn't
>used after booting under UNIX.)  So, if you can force the cache on from
>the keyboard, you should then be able to boot UNIX or XENIX with no special
>support in the kernel.
>[... u.s.w.]

	Whaattt?  Well, things never have been the same since the
	flu' hit.  Maybe the ol' brain's out the door for good.

	Well, thinking about it, my brain's DEFINITELY gone since I'm
	responding to a XENIX(rg) issue and haven't seen that sucker for
	YEARS... but... 

	Caches usually require kernel software for:
	1) Boot-time checkout (validation);
	2) Defective cache shutdown/workaround;
	3) Context-switch flushing;
	4) Memory-mapped hardware cache-BLOCKING;
	5) DMA-overlapped page flushing/blocking;
	6) Text-loading cache-flushing (split text & data caching);
	7) ... ok, my recollections are fading....

For some systems soem of the above features would be irrelevant.

Yup.  Just TURN ON THE CACHE AND RUN.  The kernel doesn't need to know
a thing about the particular cache you're using -- it uses the phase of
the moon and LORAN to work out the details.

As alluded to earlier, Bill, I can't answer if XENIX is written to
include support for the Intel cache.  It certainly COULD test for
its existence -- and run in "defective cache" mode if the cache were
absent.  But, as blithered above, I'm still dizzy from the flu'.

jcm	-- att!mtunb!jcm	-- juzz muttering... sorry... HackCoughHack