ESIX and Caching Motherboards

[James Van Artsdalen]

In <1855 at svin02.info.win.tue.nl>, debra at info.win.tue.nl wrote:

> I believe most 386 machines follow the convention that addresses with the
> most significant bit on are equivalent to the same addresses with that bit
> turned off except for bypassing the cache.

Not exactly, but close.  If the MSB is set, the cycle is not cached
and goes out to the bus - and is not decoded as a local RAM access.
That means that if you have motherboard RAM at address N, a cycle with
address N gets that RAM location, but if the MSB is set, then you get
the AT bus.

There is at least one peripheral card that depends on this scheme to
allow it to be addressed "underneath" motherboard RAM.
-- 
James R. Van Artsdalen          james at bigtex.cactus.org   "Live Free or Die"
Dell Computer Co    9505 Arboretum Blvd Austin TX 78759         512-338-8789