Determining gate depth & critical timing w/OCT tools

[Craig Pratt]

How can one determine the total gate delay of the critical path and gate 
depth of an OCT tools design?  (Besides constructing the circuit by hand from 
the BDNet file.)  I'm new to the OCT tools, and am not familiar with many
of its features.  I do know that we are using the Mississippi standard cell
library and that some obscure OCT tools are missing due to Ultrix incom-
patabilities.  *Any* recommendations are appreciated.

--
 Craig Pratt                                           icsu8053 at cs.montana.edu
 Montana State University, Bozeman MT        Craig.Pratt at msu3.oscs.montana.edu
 "It's a Buddist meditation technique; it focuses your aggression.  The monks
  used to do it before they went into battle.", Otto, _A_Fish_Called_Wanda_