All right! and 1.2M floppies; HwNote05

[John B. Milton]

I see you're all still out there.

First thing's first. If you have ANY ideas for hardware enhancements, e-mail
them off to me. Let me know about any special deals for hardware that give you
the idea and all possible uses you can think of. You will get credit for your
idea in the form of recognition, but that's all! If I sell it and make $1M,
tough luck. No flames, please. I doubt if anyone would send me any earth
shaking ideas. What I'm looking for are things like "Why don't you make a
board using the new XYZ graphics/hard-disk/tape/floppy/short-wave chip"

Well, I figured out how to get the newer generation UNIXpc mother board working
with a second hard drive. The problem is this discrepancy in the schematics.
The reference manual has two copies of the schematics, with assorted changes
between the two. The older of the two is not as old as the board I first
did the upgrade on.

The problem is the DRUN pin going to the WD1010-05. This pin needs to have a
signal from an external one-shot which is triggered whenever a pair of one or
zero bits (the same in MFM) comes in from the drive. The one shot does this by
triggering on the data signal from the 26LS32 being low for 250ns. This
separate detector is needed because the PLL (Phase Locked Loop) data separator
is not turned on yet. Once the HDC detects 8 cycles on the DRUN pin, it thinks
it has found an address mark and drives the RG (Read Gate) pin to activate the
external PLL. Once it does that, it can start interpreting the data from the
drive and start looking for sector headers.

Apparently on the old board the data signal sent to the one-shot came from
after the PAL, so it got there no matter which drive is active. The newer
board I just upgraded DOES match the schematics. The data signal goes straight
from the 26LS32 to the one-shot. They must have had some kind of delay or
stability problem going through the PAL and switched over to the raw data.
To fix the problem I had to find some way to switch which drive data is being
sent to the one-shot. It turns out there is a spare 3 input NAND gate at 13M
(pins 3,4,5,6). That must be it, 'cause it works!

The important question is whether or not there are any more incompatibilties
waiting out there. I guess the next thing is to put together a prototype
daughter board so I can get all the details nailed down. I am still considering
putting the watchdog circuit on the daughter board.

On the 1.2M floppy. Convergent cheaped out here and went with the 2797 rather
than the 2793. The reason being that they got a Side Select Output pin. What
they traded was an internal clock divide pin. This means that the clock to
the 2797 has to be externally changed from 1MHz to 2MHz when going to high
density. The VCO filter circuit (on the PUMP pin) also needs to be affected.
There are several little triangle notes around the FD about not using the
2797, but that would present another bunch of problems, ending in software.
Fortunately there is a 2MHz clock available. I think a flip flop, an open
collector buffer, a resistor and a latch should do it. The latch is already
in my current design for the second hard drive upgrade...

An interesting note: I just looked at the schematics for the floppy tape
board. They run the WD2797 in high density mode. The analog stuff on RPW, WPW,
VCO and PUMP is different. They do have a 2 MHz clock. Hmm.

I suppose what one could do would be to permanently modify the FDC to do high
density by just copying the stuff from the floppy tape. As long as you still
have access to a system with a low density setup you could access low density
disks. With a 1.2M disk you could mount the floppy on /usr/spool/news and
expire once an hour :)

Next time: 4M machine with a 1.5M Combo card (maybe)

John
-- 
John Bly Milton IV, jbm at uncle.UUCP, n8emr!uncle!jbm at osu-cis.cis.ohio-state.edu
home (614) 294-4823, work (614) 764-4272;  Send vi tricks, I'm making a manual